recovery n. 1.重獲;復(fù)得;恢復(fù),收回,回收。 2.還原,復(fù)原;痊愈;蘇生;矯正。 3.回縮。 4.填地。 5.【法律】勝訴。
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例句與用法
Clock recovery , cdr 時(shí)脈恢復(fù)電路
In this paper , a clock recovery system that based on phase control technology is studied 本文設(shè)計(jì)的鎖相環(huán)路是基于相位控制技術(shù)的時(shí)鐘恢復(fù)系統(tǒng)。
The clock recovery system is fabricated in tsmc 0 . 25um cmos process . simulation in smartspice shows that the circuit as expected 設(shè)計(jì)中采用tsmc0 . 25umcmos工藝,用smartspice進(jìn)行設(shè)計(jì)仿真和優(yōu)化。
In the last part of this paper , simulation is given to show the performances of the clock recovery methods . the results prove the good jitter performances of the methods 從仿真結(jié)果可以看出,同步時(shí)鐘統(tǒng)計(jì)恢復(fù)法具有很好的抖動性能,可以作為gpon系統(tǒng)tdm接入的一種高效時(shí)鐘恢復(fù)方案。
Clock recovery is an important and difficult part of tdm access , so the thesis will emphasize on it . and two methods of clock recovery are proposed in the thesis 然后,本文對同步時(shí)鐘統(tǒng)計(jì)恢復(fù)法進(jìn)行了分析,推導(dǎo)出了時(shí)鐘信號低頻抖動的時(shí)域和頻域特性公式,并利用matlab對低頻特性進(jìn)行了仿真分析。
Gpon is multi - point to point network topology structure in upstream direction . in order to transmit tdm services , besides the common modules such as dba , fec , aes , the system also need data adjustment , clock recovery , and so on 其中同步時(shí)鐘恢復(fù)是實(shí)現(xiàn)tdm接入的重點(diǎn)和難點(diǎn),因此本文重點(diǎn)討論了同步時(shí)鐘恢復(fù)的方法,在研究atm和sdh時(shí)鐘恢復(fù)方法的基礎(chǔ)上,提出了同步殘余時(shí)標(biāo)法和同步時(shí)鐘統(tǒng)計(jì)恢復(fù)法。
In this paper , the design of a specific chip for circuit emulation based on ip is put forward and realized and the main functional modules and the key algorithms including an all - digital adaptive clock recovery method and a dynamic depth buffer algorithm are described in detail 文章根據(jù)相關(guān)標(biāo)準(zhǔn)提出并實(shí)現(xiàn)了一種電路仿真專用芯片的設(shè)計(jì)方案,并對其中主要功能模塊和關(guān)鍵算法作出了詳細(xì)說明,包括一種全數(shù)字的自適應(yīng)時(shí)鐘恢復(fù)方法、動態(tài)深度緩沖算法等。
The clock recovery block of usb2 . 0 transceiver macrocell consists of phase locked circuit , such as pll and dll ( delay locked loop ) . this block use external crystal 12mhz sin signal to produce 60mhz , 120mhz , 480mhz clock signal , and can recover colock signal form date wave . it can support 480mbps ( hs ) and 12mbps ( fs ) word speeds as defined in usb2 . 0 specification . 目的是用鎖相環(huán)電路? pll和dll (延遲鎖相環(huán))實(shí)現(xiàn)usb2 . 0收發(fā)器宏單元utm的時(shí)鐘恢復(fù)模塊。其中pll環(huán)路構(gòu)成的時(shí)鐘發(fā)生器將外部晶振的12mhz正弦信號生成60mhz 、 120mhz 、 480mhz等本地時(shí)鐘信號。 dll環(huán)路依據(jù)本地時(shí)鐘信號對外部數(shù)據(jù)信號進(jìn)行時(shí)鐘恢復(fù)。